1. Field of the Invention
The present invention relates to a technique of reducing an output offset in an input/output circuit, particularly in a magnetic read/write circuit.
2. Description of the Background Art
FIG. 7 shows an exemplary structure of a part, which is related to a reproducing circuit, of a conventional magnetic read/write circuit. Center taps of heads 3 and 6 (HD3 and HD6) are connected in common and biased to a potential V.sub.CT through a power source 4. The heads 3 and 6 are connected to differential input ends of amplifiers 2 and 5 respectively. Differential output ends of the amplifier 2 are connected to first ends of resistors 7 and 8 through lines 9 and 10 respectively. Differential output ends of the other amplifier 5 are also connected to the first ends of the resistors 7 and 8 through lines 11 and 12 respectively. Second ends of the resistors 7 and 8 are connected to a power source 1.
The lines 9 and 11 are connected to a differential input end of an output stage amplifier 19 through a buffer 15 and a line 17, while the lines 10 and 12 are connected to another differential input end of the output stage amplifier 19 through a buffer 16 and a line 18. A differential output end of the amplifier 19 is connected to the power source 1 through a line 20 and a resistor 22, while another differential output end is also connected to the power source 1 through a line 21 and a resistor 23. The lines 20 and 21 are provided with output terminals 26 and 27 (RDX and RDY) respectively.
The amplifiers 2 and 5 are driven and stopped by control switches 24 and 25 respectively. These control switches 24 and 25 are controlled by a control circuit 30 through control lines 28 and 29 respectively. The control circuit 30 is provided with a read/write switching terminal 31 which receives a read/write switching signal R/W, a head selection input terminal 32 which receives a head selection signal HS, and a chip disable control terminal 33 which receives a chip disable signal CD respectively.
In the reproducing circuit having the structure shown in FIG. 7, offset fluctuation disadvantageously appears at the output terminals 26 and 27 in head switching, read/write switching and chip disable switching operations. With reference to FIG. 8, this problem is now described in detail as to the respective operations.
A. In Head Switching Operation (refer to FIG. 8(a))
The head selection signal HS is inputted in the control circuit 30 to turn the control switches 24 and 25 on/off, thereby selecting only one of the amplifiers 2 and 5 for switching the heads. When the head 3 (HD3) is first selected in read mode, the amplifiers 2 and 5 are turned on and off respectively. At this time, the total offset of two-stage amplifiers, i.e., the amplifiers 2 and 19, appears at the output terminals 26 and 27. Referring to FIG. 8, symbol L1 represents the level of this total offset.
When the head 6 (HD6) is selected, the amplifiers 2 and 5 are turned off and on respectively. At this time, the total offset of the two-stage amplifiers, i.e., the amplifiers 5 and 19, appears at the output terminals 26 and 27. Referring to FIG. 8, symbol L2 represents the level of this total offset. When the head 3 is again selected, the offset appearing at the output terminals 26 and 27 returns to the level L1.
When the offsets of the amplifiers 2 and 5 are different from each other, this difference is further increased by the amplifier 19 to vary the offset appearing at the output terminals 26 and 27. Thus, offset fluctuation is caused by a head switching operation.
B. In Read/Write Switching Operation (refer to FIG. 8(b))
When the head 3 (HD3), for example, is selected, the read/write switching signal R/W is inputted in the control circuit 30, to switch a write operation (denoted as "W" in FIG. 8(b)) by a write circuit (not shown in FIG. 7) and a read operation (denoted as "R" in FIG. 8(b)).
As described in the above item A, the offset appearing at the output terminals 26 and 27 is at the level L1 in the read operation. When the operation is switched to write mode, the control switch 24 is also turned off similarly to the control switch 25, whereby only the offset of the amplifier 19 appears at the output terminals 26 and 27. Referring to FIG. 8, symbol L3 represents the level of this offset. When the operation is again switched to read mode, the offset also returns to the level L1.
Therefore, the offset appearing at the output terminals 26 and 27 is varied with switching between read and write operations.
C. In Chip Disable Switching (refer to FIG. 8(c))
When the signal CD is inputted in the control circuit 30 to implement a chip disable state, both amplifiers 2 and 5 are turned off. IF a chip disable state is implemented when the head 3 (HD3) is selected for read mode, therefore, offset fluctuation appears at the output terminals 26 and 27, similarly to the case of the above item B.
As described above, the output offset of the conventional magnetic read/write circuit is disadvantageously varied with switching between various modes.